2019/07/03 (Wednesday)
| Setup | DIB1/3/4 → 3.2 MHz filters 2/3/1 → cable 3/1/2 → gender changer ?/3/2 → HVConn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC55(1) DCRC33(2) → 1kV power supply → HV input Three walls of the lead/poly shield are up. |
|---|---|
| 0850 | Tower/MC/Coldplate = 38.8/29.4/197 mK, Still = 1.36 K / 0.18 mbar / 6 mW, G1/G2 = 197.1.1/190.5 mbar, 1K Pot = 1.615 K / 19 mbar. MB = 69.1% |
| 0930 | Attempted to fill LN2 Cold trap but there was some kind of blockage. |
| 1510 | Fill LN2 cold trap from transfer dewar. |
| 1630 | Experiment with DCRC1pD trigger threshold, with the new trigger length settings. It looks like a threshold of 3 starts to dip into the noise. We'll try that. |
| 1643 | Start a sequence of 6 @ 87 min series at HV = 180→400V, rate 2.49V/min, with 10% prebias for 2 minutes, flash at end with 30 min wait. CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/495)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5) 1000 BOR, 5Hz InRun randoms, trigger on DCRC1pD threshold = 3, baseline/sample length = 20/30 (standard 5/16), phonon pre-pulse 600 (standard is 500). Use sequence HVdrift_6X180V_2p49VPM_loopversion_prebias_10_2_dur_87min_flashDCRC_1_4.msl |