2019/07/1 (Monday)
| Setup | DIB1/3/4 → 3.2 MHz filters 2/3/1 → cable 3/1/2 → gender changer ?/3/2 → HVConn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC55(1) DCRC33(2) → 1kV power supply → HV input Three walls of the lead/poly shield are up. |
|---|---|
| 0840 | Tower/MC/Coldplate = 40.2/29.9/198 mK, Still = 1.67 K / 0.18 mbar / 6mW, G1/G2 = 216.3/204.7 mbar, 1K Pot = 1.61 K / 19.0 mbar. MB = 71.5% |
| 0850 | Fill LN2 cold trap bath from transfer dewar. |
| 1540 | Fill LN2 cold trap bath from transfer dewar, dewar empty mid-transfer reconnect main dewar and finish from there |
| 1654 | Start a sequence of 6 @ 87 min series at HV = 180→400V, rate 2.49V/min, with 10% prebias for 2 minutes, flash at end with 30 min wait. CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/495)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5) 1000 BOR, 5Hz InRun randoms, trigger on DCRC1pD threshold = 6. Use sequence HVdrift_6X180V_2p49VPM_loopversion_prebias_10_2_dur_87min_flashDCRC_1_4.msl |
- Leakage kept increasing during this sequence, Vtest max = 9/12/14/22/24/25 mV