| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| 1310 | Fill LN2 cold trap full. |
| 1311 | Tower/MC/Coldplate = 32.8/30.8/196 mK, Still = 1.27 K / 0.110 mbar, G1/G2 = 216/210 mbar, 1K Pot = 1.675 K / 24.0 mbar. Main Bath = 62.9% (predicted level: 66.2%) |
| 1314 | HV = 103.9 V, Vtest = 10.47 mV → Vdetector = 99.71 V |
| 1320 | Dial HV down to zero and short leads. |
| 1323 | Start 30 minute bake with DCRCs 1&2 |
| 1408 | Dial HV up to 20.0 V. |
| 1418 | Dial HV down to 10.01 V |
| 1428 | HV = 10.01 V, Vtest = 0.14 mV → Vdetector = 9.95 V |
| 1432 | Start 18 1-hour data series (start #6748) of 1-sided 10 V data with Frontend Gain = (15/15/5)/(5/4/4), OG = 4/2, QET biases set with the Ib*pf=30 values in table from May 24, with 1000 beginning randoms, no flashing, and a 24 ADC bin threshold trigger on DCRC1 pA (Side1 pE). |
| 1721 | Adjust ADCoffset on DCRC2pC from 0 to -0.05. I noticed that DCRC2pC has it's baseline too high, pulses show ADC saturation. |
| 1726 | Adjust ADCoffset on DCRC2pC from -0.05 to -0.12 |
| | Starting Dump 54 in series _1632, the DCRC2pC baseline is now low enough not to saturate. |