| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| 0850 | Tower = 33.0 mK, Main Bath = 67.0% |
| 0855 | Fill LN2 cold trap bath |
| 1015 | Attempting to find source of 7 kHz noise seen in all phonon channels in current setup. Unplug TTL signal line leading from NaI electronics to DCRC4 and use randoms trigger. Noise remains. |
| 1034 | Stop DCRC programs, change DCRC1 to timing master, DCRC2,4 to slaves. Restart programs, noise remains. Unplug HV cables from HV board, no change. |
| 1043 | Unplug timing link cables while looking at randoms, no change in noise. |
| 1045 | Reset iming link manually with DCRC1 as master, no change. |
| 1046 | Note that the 7 kHz is NOT observed in DCRC4pB. This is just open to the LED2 pins at the board, but perhaps it means the noise is introduced upstream, or perhaps without the whole feedback circuit, it's just not sensitive to it. |
| 1053 | Disable and power down DCRC4, remove its timing link cable. Noise still observed in DCRC1,2. Re-enable DCRC4, re-connect it's timing link, and make it the timing master again. |
| 1110 | So, it turns out DCRC2pC has been set to open loop for a while. Changing this back to non-inverting gets rid of the 7kHz signal for all phonon channels, even those on DCRC1. Will have to think a bit about what's going on here. |
| 1423 | Tower/MC/Coldplate = 33.4/31.0/187 mK, Still = 1.2 K / 0.110 mbar, G1/G2 = 250/241 mbar, 1K Pot = 1.689 K / 28 mbar. Main Bath = 58.7%. Boil off rate: close to slow mode (predicted level: 59.9%) |
| 1500 | Remove Y88 source from safe. Suspend it on meter stick from the south wall of the shield. |
| 1646 | Start 1 hour 0V test coincidence series with 1500 ADC trigger on DCRC4pA (TTL signal) OR of both NaI detectors. |
| 1747 | Fill LN2 cold trap. |
| 1756 | Start 1 hour 0V test coincidence series with 1500 ADC trigger on DCRC4pA (TTL signal) single NaI detector. |