| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 → gender changer 3/1/2 → DCRC55(1)/33(2)/X(4) |
| 0900 | Tower = 43.0 mK, Main Bath = 38.0%. |
| 0900 | Disable 15V power on DCRC2 (/ Equipment / Tower01 / Settings / DCRC2 / LED / Enable15VPower = n). Tower temperature immediately drops. Settles at around 34 mK after 4 minutes. |
| 0910 | Tower = 33.5 K |
| 0910 | Disable 15V power on DCRC4. This causes small temperature increase, to 34.0 mK. Turn it back on. Temperature seems to come back down. |
| 0930 | Tower = 33.3 mK |
| 0935 | Fill LN2 cold trap bath. |
| 0940 | Tower = 32.8 mK after LN2 fill |
| 1424 | Tower/MC/Coldplate = 33.3/31.0/189 mK, Still = 1.2 K / 0.120 mbar, G1/G2 = 246/227 mbar, 1K Pot = 1.694 K / 30 mbar. MB = 29.5%. Boil off rate: slow mode (predicted level: 29.6%). |
| 1439 | Start LHe transfer (MB = 29.3%) |
| 1630 | Finish IbIs on DCRC2pB/DIB2pB/Side2pA |
| 1655 | Finish IbIs on DCRC2pC/DIB2pC/Side1pA |
| 1705 | Finish LHe transfer (MB = 91.1%) |
| 1710 | The DCRCX channels can't take nearly as high front-end gains as the DCRC1 channels. pB/C/D are limited to around 3/3/4. We should check what size filter resistors this board has. |
| 1742 | Fill LN2 cold trap full. |
| 1749 | Tried to do IbIs on DCRC4PB/DIB4pB/Side1pF but every time QET bias reaches 140 uA, channel rails. Tried relocking a few times and restarting curve, but each time it railed when going from 160 uA to 140 uA, so I gave up. |
| 1815 | Finish IbIs on DCRC4pC/DIB4pC/Side1pC |
| 1845 | Finish IbIs on DCRC4pD/DIB4pD/Side1pF |