| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| 0935 | Tower/MC/Coldplate = 33.6/31.4/194 mK, Still = 1.3 K / 0.120 mbar, G1/G2 = 245/225 mbar, 1K Pot = 1.702 K / 32 mbar, Main bath = 30.5%. Boil off rate: close to slow mode (predicted level: 33.7%). |
| 0940 | Fill LN2 cold trap bath. |
| 1152 | Start LHe transfer (MB = 26.8%) |
| 1258 | End LHe transfer (MB = 90.5%) |
| 1535 | Finish IbIs on DCRC1pA/DIB1pA/Side1pE. At the standard bias of 130.2 the Ib*prefac is now 33.7 uA, used to be 40 uA. To get to 40 uA according to this new IbIs should adjust QET bias to 132.7 uA. |
| 1609 | By measuring superconducting slope at 3 different gains, verify that Rev.C driver gains (1-3) are linear within 1% (yay!) |
| 1700 | Finish IbIs on DCRC1pB/DIB1pB/Side1pB. At the standard bias of 143.2 the Ib*prefac is now 33.7 uA, used to be 43 uA. To get to 40 uA according to this new IbIs should adjust QET bias to 145.3 uA. |
| 1725 | Finish IbIs on DCRC1pC/DIB1pC/Side1pD. At the standard bias of 130.4 the Ib*prefac is 39.4, this is within error equal to the target value of 40. |