| 0911 | MC/Tower = 52/71 mK. G1/G2 = 276/258 mbar. Still = 4 mW / 1.08 K / 0.19 mbar. 1K Pot = 1.70 K / 20 mbar. Cold plate = 9.56 kΩ / 304 mK. MC sensor = -38.56 kΩ / 70 mK. Main bath = 21.7%. |
| 0930 | Fill LN2 cold trap full. |
| 0933 | Set up to take noise PSDs on DIB1 with DCRC50 (not other DCRCs connected). Zap SQUIDs and set optimal lock points and QET biases. |
| 0936 | Set Front End Gains to 50 and Output Gains to “3”. Had to adjust Driver Offsets of pB, pC, pD to 0.060, 0.040, and 0.040 V respectively. |
| 1005 | Problems with pC offset, trace slips out of range. You can see the baseline creep upwards and sometimes jump downwards. Had to reset offset to 0.120 V to avoid railing. Baseline drifts down to -0.1 V then stable, then jump to -0.05 V, then creep upward. |
| 1024 | Finish saving noise PSDs for DIB1. |
| 1338 | Attempting to set up three simultaneous DCRCs. Here's what we already know: |
| DCRC issues this run |
| DCRC31 | v. C | Can't communicate if it is sharing the ethernet switch with DCRC33 |
| DCRC33 | v. C | no obvious problems |
| DCRC50 | v. C.1 | Can't use on DIB1 because the “interference problem” is very bad |
| DCRCX | v. C.1 | (this is the one from Soudan whose SN is unknown) No test signal, so can't set DCRC-specific SQUID lockpoints. |
The images below are screen caps of the interference problem as it appears in the charge traces. In this case the phonons are flatlined, which occurs when the interference appears if they are set to high gains: otherwise we typically see pulse-less noise in the phonons. The images are from DIB1/DCRC33. The traces in the other DIBs show similar behavior when the interference problem is present. Click images for large version.
| Figure 1: Interference pattern in charge traces |
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| Figure 2: Time scale zoom: frequency apparently around 110 kHz |
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| Figure 1: Tighter time scale zoom |
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We tried to find a configuration in which we could run with three DCRCs. But in many cases the interference problem was persistent whenever the DIB1 FETs were powered. These are labeled “bad” below. In other cases the DIB1 FETs could run and signals be seen for a certain amount of time, typically 20 seconds, before the interference problem appeared, and it was then fixable with a FET power cycle. These are labeled “mediocre” below. In a few cases the DIB1 FETs could be powered indefinitely with no interference problem. These are labeled “OK” below.
| Attempted DCRC configurations |
| DIB1 | DIB2 | DIB3 | status | notes |
| DCRC33 | DCRC50 | DCRCX | bad | |
| DCRC33 | DCRC50 | none | OK | also seemed OK with +1/-1 V bias, but mediocre at +3/-3 V bias |
| DCRC33 | DCRCX | none | OK | noted here and later that interference can be induced by simply plugging anything into a DIB port on the ebox, even unpowered. |
| DCRC33 | DCRCX | DCRC50 | bad | |
| DCRC33 | none | DCRC50 | bad | |
| DCRC33 | none | DCRCX | mediocre | |
| DCRC33 | ground | DCRCX | mediocre | “ground” refers to grounding plug. |
| DCRCX | none | none | bad | For DCRCX in DIB1, Qi was flatline until resetting Qi Offset to -1.00 V |
| DCRCX | ground | none | OK | |
| DCRCX | DCRC33 | none | OK | |
| DCRCX | DCRC33 | ground | bad | |
| DCRCX | DCRC33 | DCRC50 | mediocre | noticed that simply adjusting Qo offset seemed to induce interference |
We concluded that no 3-DCRC mode could be run stably.
| 1555 | Commence LHe transfer (7.9%). |
| 1612 | Bench tests of DCRC31 communication problem: it is OK when sharing the ethernet switch with either or both of the v. C.1 DCRCs (DCRC50 and DCRCX). But it won't communicate when sharing with DCRC33. When DCRC33 is plugged in, DCRC31 communications cease after a few seconds: commands in the Putty Telnet session simply hang. When DCRC33 is then unplugged, after a few seconds DCRC31 answers the query it hung on and is communicative again. |
| 1658 | Preparing to set up for data taking with two DCRCs: DIB1=DCRC33 and DIB2=DCRC50. |
| 1702 | Zap all SQUIDs twice. Set optimal SQUID lockpoints and QET biases (for DIB1/DCRC33 use the QET biases calculated with DCRC50 but with signs reversed). |
| 1738 | Set all QET gains to Frontend=50, Output=“3” (not sure what this means on v. C but on v. C.1 this is supposedly a gain of 8). Had to set Driver Offsets on DIB1 pA, pB, pC of 0.100, -0.010, 0.100 V respectively to avoid flatline. |
| 1751 | Establish timing link between DCRCs |
| 1815 | Attempted setting +3 V charge bias on DIB1 as test. Not surprisingly this induced the interference problem. The interference was fixable but unfortunately it caused all phonon channels to flatline, necessitating going through them all again and fiddling with gains and setpoints. |
| 1826 | Fill LN2 cold trap full. |
| 1845 | Interference appeared a couple more times. Got tired of struggling to set things up. Can't run stably with bias on crystal, so can't do seagull plot. In principle could look at phonon pulses with zero-bias. Maybe will try this Monday. |
| 1850 | End LHe transfer (68.2%). |