2015/05/14 (Thursday)
| 0900 | MC/Tower = 53/76 mK. G1/G2 = 279/255 mbar. Still = 4 mW / 1.13 K / 0.19 mbar. 1K Pot = 1.71 K / 20 mbar. Coldplate = 9.48 kΩ / 307 mK. MC sensor = -38.3 kΩ / 70 mK. Main bath = 67.4%. |
|---|---|
| 0925 | Fill LN2 cold trap full. |
| 1120 | Finish IbIs measurement on DIB3 with DCRC50. 0 to 600 μA in 3 μA steps. |
| 1250 | While measuring IbIs on DIB1 with DCRC50, channel C railed at bias points above 10 μA. Applying a driver offset of 0.03V fixed the problem. |
| 1335 | Finish IbIs measurement on DIB1 with DCRC50. 0 to 600 μA in 3 μA steps. |
Used DCRC50 to produce IbIs curves out to 600 μA on all three DIBs, because we want to use DCRC50 to study noise and we want optimal QET settings. Calculated the optimal biases using the following method:
- Fit a line to the normal-resistance portion of the curve (high bias) and extend to Ib=0
- Construct a second line with the same Ib=0 intercept as the previous but with slope 4 times greater
- Where the second line intersects with the IbIs curve, use this Ib value as optimal QET bias current
Also shown in the table below are the critical currents as read off of the IbIs curves: the Ib value at which the curve abruptly changes to superconducting behavior.
For DIB1 phonon channel D the Ib range in the IbIs curve was insufficient to get a good read on the normal-resisting part (it seems to have a particularly large Rn). So instead the optimal setting below is based on the critical current: for the other eleven channels I fit a line to Iopt versus Icrit and found a strong correlation, so I chose the DIB1 pD Iopt value accordingly.
| Optimal QET bias currents using DCRC50 | |||
|---|---|---|---|
| DIB | QET | Optimal bias (μA) | Critical current (μA) |
| 1 | A | 216 | 140 |
| 1 | B | 180 | 140 |
| 1 | C | 179 | 113 |
| 1 | D | 205* | 128 |
| 2 | A | 133 | 93 |
| 2 | B | 108 | 71 |
| 2 | C | 114 | 85 |
| 2 | D | 162 | 113 |
| 3 | A | 117 | 89 |
| 3 | B | 175 | 128 |
| 3 | C | 154 | 104 |
| 3 | D | 122 | 95 |
| 1544 | Set DIB2 (DCRC50) QETs to optimal biases. Set all four DIB2 phonon channels to Frontend Gain = 50, Output Gain = “3” (which means a gain of 8 on vC.1). |
|---|---|
| 1624 | Took noise PSDs of phonon channels for DIB2-DCRC50. Set trace window to 10 ms and took PSDs of individual traces, picking only traces with no pulses. Saved 5 of each. (It would be nice to modify the LabView vi so that it would average several PSDs but only from pulses chosen by the user.) |
| Note: | The DIB2/DCRC50 noise PSDs were taken with DCRC33 plugged into DIB1 and the timing link established. |
| 1625 | Move DCRC50 to DIB3, remove DCRC33. Zap SQUIDs twice, lock SQUIDs, apply optimal QET biases. |
| 1644 | Set all four DIB3 phonon channels to Frontend Gain = 50, Output Gain = “3”(8). |
| by default the Driver Offsets were left at 0. However for B, it was necessary to set the Driver Offset to 0.01 V to prevent railing. | |
| problem with C: at Frontend Gain of 50 could not find a driver offset that avoided railing the signal. So for C used Frontend Gain of 30 and Driver Offset of 0.87 V (quite high). Also this setpoint appeared unstable - the Driver Offset had to be readjusted occasionally. | |
| 1710 | Fill LN2 cold trap full. |
| 1742 | Finish DIB3/DCRC50 noise PSDs. |