| 0930 | The -4V test data took last night look good. Trigger threshold can be set at 9, 10, 16, and 16 ADC bins for Q1 to Q4. |
| 1048 | The trigger rate was very low after random triggers at -7V bias and soon the connection to DCRC30 was reset. The board connected to POE P72505597A1 always has some problems from time to time. This could be due to the switch or the POE itself. I'll try a different switch port. |
| 1057 | Trigger rate is at ~4Hz, still low. |
| 1100 | Found DCRC30 had no response to trigger settings. This is communication problem. This might be due to the POE. |
| 1206 | Take data 07110626_1204_F0001. -7V on Q1-4. Trigger rate was recovered. ~45Hz. DAQ trigger was too low was probably because the trigger threshold was too low and the DAQ could not handle the triggers. Take 10min data and flash for 6s to have a look at the noise. |
| 1418 | The trigger rate is fixed by setting the trigger threshold at mean(Qstd)+30sigma(Qstd), (26, 32, 38, 30) ADC bins for Q1-4. Baseline noise is too large. Series 07110626_1414 |
| 1450 | Start to take bias sweep data 07110626_1450_F0001. Calibrate -7V on Q1-4. Trigger on Q1-4 at (26, 32, 38, 30) ADC bins. Trace length 0.4096ms, lookback time 100us. Data/flash/cooldown = 30min/6s/20min. Tower temperature 59.5mK. 4 series per bias. |
| 1900 | Filled N2 cold trap. |