2010-12-21
| SqA of DCRC30 lost lock easily. It may be a better idea to add feedback null to adjust the dc level instead of using lockpoint in closed loop. | |
| 0050 | DCRC30 charge pulses jump around in time domain. The trigger doesn't seem work properly. |
| 1213 | Phase lock between two boards are OK. Both can be slave/master. Address 15, slave reads 02B0 and master reads 02A1. |
| Can use the command fr to check the checksum to check the software version | |
| Charge digitizer resolution 4V/2^16 = 61.035uV , phonon 2.5V/2^14 = 152.587890625e-6V | |
| The board can be tested on bench, but need to turn off the 15V charge amp power supply by wr 30 0 | |
| 1512 | Try to test triggers on DCRC30. See funny noise on both boards. Cycle the power. |
| 1515 | Power on DCRC30 on G9 |
| 1533 | Because of noise, power off DCRC30 |
| 1539 | Power on DCRC30 on G9 and apply -3V to Qi and Qo, charge triggers work as expected. There were low frequency oscillation noise when the power supply wasn't grounded. |
| 1545 | Charge triggers on DCRC33 also work. |
| 1550 | After setting the timing link both charge triggers work. DCRC30 was master and DCRC33 was slave. Address 15 reads 221 on the master and 02B0 on the slave. |
| The charge channels have 75mVrms noise. Most phonon channels have rms noise 8mV with output gain 7 | |
| The big noise in charge channel disappeared after a spark produced when disconnecting the power supply ground. Now both boards are ungrounded. | |
| Maybe the following procedure would be able to get rid the noise |
- Plug in both boards and connect the timing link cable. Don't power up them yet
- Power up one board, check the charge noise on the readout vi, if it's OK then power up the other board
- If the noise didn't change when the other board is on, then it means the big noise didn't show up.
| 1637 | Zap all squids on DCRC33, G8 |
|---|---|
| 2300 | Timing link between boards is essential to reduce noise. |
| G8 DCRC33 | |||||||
|---|---|---|---|---|---|---|---|
| Channel | Frontend Gain | Output Gain | Driver Offset [V] | SQUID Bias [μA] | Lockpoint [mV] | QET Bias [μA] | Mod. Depth |
| A | 1 | 1 | 0 | 85 | 3.12 | -80 | 260 |
| B | 1 | 1 | 0 | 72 | 1.75 | -70 | 250 |
| C | 1 | 1 | 0 | 83 | 3.89 | -80 | 360 |
| D | 1 | 1 | 0 | 84 | 3.89 | -80 | 84 |
| G9 DCRC30 | |||||||
|---|---|---|---|---|---|---|---|
| Channel | Frontend Gain | Output Gain | Driver Offset [V] | SQUID Bias [μA] | Lockpoint [mV] | QET Bias [μA] | Mod. Depth |
| A | 1 | 1 | 0 | 82 | 5.16 | -80 | 410 |
| B | 1 | 1 | 0 | 96 | 5.35 | -120 | 520 |
| C | 1 | 1 | 0 | 96 | 5.06 | -160 | 470 |
| D | 1 | 1 | 0 | 85 | 2.92 | ? | 390 |
| 2300 | When Trigger FIFO (bit 8, register 15) is full, we get a lot of rubbish. One way to avoid this is to set the trigger threshold high enough to prevent saturation of the buffer. This can be determined by the command rd 29 to output the content of the buffer. The value should not deviate too far from 0 (need to enter it a few times). Strangely, DCRC33 dealt comfortably with a phonon channel threshold of 3.5 mV, but DCRC30 required a higher threshold of 14 mV. Maybe because of the presence of the source below G9, but such a feature was seen yesterday when DCRC30 was connected to G8. It is likely that the trigger on the board is faulty. |
|---|---|
| Data taken: 8 files; event rate 15-20 Hz; 07101221_2209. DAQ settings and Trigger settings | |
| 2331 | Stop the run 07101221_2209 at file 9 |
| 2341 | Ground two detectors and flash them with LED1 -0.4mA, ON 100us ,OFF 200000us |