2010/12/20

1135	Power up DCRC30 and 33. A temperature spike shows up.
	Write wr 15 20 to both boards and both can read data correctly. Now try to set the timing link.
	Used the following procedure to set the timing link and it worked. Set Bit 2 of address 15 to 0, or subtract 4 from the old command data.

1148	With -3V bias on both charge channels. DCRC33 has a noise floor of about 6mV, which corresponds 30keV. The beating pattern is still there. Now ground the detector and have a look at the phonon channels again.
1647	Turn off the 15V charge amp power supply on both boards will get rid of the low frequency beating noise. Set Bit 15 of address 30 to 0. They have to
	VGA gain should be as high as possible without causing oscillations. May be able to see this oscillation in phonon PSD. Higher bandwidth introduces more noise to the phonon signal. Digital filter is needed when processing the data.
	When the FET are frozen, the 15V charge amp will heat up the fridge. Need to turn on the FET heater to get rid of the heating.
1705	Fill N2 cold trap full
2024	Power up the boards without power grounds and timing link. Can see charge signals after writing wr 15 0, and wr 15 20 on both boards.
2131	If use the closed loop lockpoint to adjust the DC level, the DC level change caused by QET bias would easily saturate the ADC at output gain higher than 2.