DCRC v3

• RevC.0 Register Map
• RevC.1 Register Map

See procedure:setting_up_dcrc_boards for more info on board ip addresses, etc.

<note> In the new firmware, all commands send to address 15 should subtract 4 from the old value. </note>

Need to use 'wr 15 4; wr 15 24' to turn on DCRC clock after resetting it

wr 15 4
wr 15 24

Need to use 'wr 15 0; wr 15 20' to turn on DCRC clock after resetting it after firmware change.

wr 15 0
wr 15 20

Connect the cable… Far is away from the master timing. Near is toward the master timing board. The master timing board should have a cable connected to ‘far’ and not to ‘near’.

1) Turn off 50 MHz clock on all boards. Ie:

wr 3c 0

2) For the slave boards. Set the PLL reference source:

3) For the master board. Toggle the write enable.

• Connect mini Break Out Box (miniBOB) to D50 connector of unpowered DCRC.
• Connect ethernet cable to power and communicate with DCRC.
• Using Detector Control VI, apply Q-bias values from -14V to +14V in steps of .5V
• Measure and record voltages on miniBOB outputs: Qi to GND and Qo to GND.
• Plot and fit Actual Output Voltage vs. Intended Output Voltage.
• Use fit to compute Nominal Output Voltage needed to achieve Actual Output Voltages from -14V to +14V in steps of .5V for both Qi and Qo.

<note> 2011-04-15, 20:19
HP3478A DC voltage measurement was found to be off by a few to a few tens of milivolts depending on the voltage it measured. Fluke 177 and RMS225 got close enough values though RM225 reading was a little bit lower. Fluke 177 may be the most accurate one available at hand. So I used it to do the calibration again. </note>

Calibration data fits

HP3478A gave the same numbers of DCRC30 Qi output when the board was connected to nothing as when the board was connected to the detectors in the last calibration. The effect of the detector as a load is not significant. The results of last calibration is still valid, especially at low biases.

Since HP3478A has quite a bit offset in voltage measurement. I stopped using it after this comparison.

<note> Use this table to set the DCRC biases </note>

The field leakage of g101 was measured during the warm up at 53K. This temperature was already higher than the freeze temperature of the outer channels. But the result may still be useful. The connections were: DCRC33 Qi→Q1, Qo→Q3; DCRC30 Qi→Q2, Qo→Q4. I adjusted the bias on Q2 and Q4 and measured the voltage of the other channels. Because Q2 and Q4 were on the same board and the both biases were kept at a constant by the board, the leakage between them could not be measured. It might not be a good idea to have the second board connected to the detector when measuring the leakage because the output impedance of the charge bias circuit may change the result. But this is the configuration one has to use when doing the experiment.

Once again, the output was not affected whether the board was connected to the detector. Q2 and Q4 had the same leakage to Q1; they also had the same leakage to Q3, which was about twice as large.

TPS2024 x1 Probe.

From Confluence Note written by Scott Oser.

First, some general notes. A test signal generated on the DCRC, under firmware control, may be connected to either a QET or to a phonon readout channel. In spite of what the DCRC register map notes say, this version of the DCRC does not use the AD5932 chip to generate the test signal, although parts of the very awkward user interface for that chip are used for controlling the test signal still. (This chip was apparently used for DCRC v3.0, but in v3.1 instead the chip is partly emulated in firmware.)

The only signal shape available at present is a triangular wave. This is a significant limitation, since some tasks like complex impedance measurements require a square wave. But a triangle wave should be OK for things like Ib/Is.

The user can control the amplitude and frequency of this wave.

In the MIDAS ODB the amplitude is controlled by the key TowerXX/Settings/DCRCYY/TestSignal/DDSStartFreq . With older version of the Rev C.1 firmware (before April 2014) it doesn't seem possible to change the frequency while the test signal is running, but this seems now to work for the most recent firmware that Sten produced in April 2014. So for boards running older firmware you need to program the frequency before starting the test signal. An unfortunate issue is that it doesn't seem possible to turn off the test signal without rebooting the board, under the older firmware. (You can however disconnect it from the phonon or QET channels, but the test signal may still be running on the board.) This ODB key is mapped to DCRC registers 0x42 and 0x43. These are actually 12-bit registers that store the lower and higher bits of the 24-bit frequency setting. The actual frequency you get from the board is the clock frequency (40MHz for RevC, 50MHz for RevC.1), times the 24-bit frequency setting divided by 2^24. So If you load the registers with 1000, that will create a test signal with frequency of 40MHz*1000/2^24 = 2384Hz. Note that for a Rev C board the frequency will be higher by a factor of 50/40.

This was much easier to control, by altering the ODB key TowerXX/Settings/DCRCYY/TestSignal/DDSDACScaling . Changes to this setting do take effect while the signal is already running. The register map says this about the scale, which I haven't tried to verify: “A 10 bit DAC value of 0x000 to 0xFFF scales the DDS output from 6mV to approximately 6Vpp. Internally, the DAC ignores the two lower order bits in the data field. This voltage is divided by 5 when connected to the phonon feedback amplifiers. It is routed through 10K ohm resistors when connected to the QET bias.”

Older firmware (pre-April 2014): To start the test signal, you have to toggle the key TowerXX/Settings/DCRCYY/TestSignal/DDSControlPin from off (N) to on (Y). This is an edge-sensitive trigger—-it's the transition rather than the level that starts the signal. I believe that when the board reboots the signal is always off, so the first time you set this bit to on it will start the test signal. Inside the DCRC this is register 0x3c, bit 13. Unfortunately, toggling the bit back to off does not stop the test signal. It is not possible to stop it, seemingly.

Newer firmware (post-April 2014): To enable the test signal, you write to bit 10 of register 0x3d. To turn it off you set this bit to zero. It is not necessarily safe to change the values of the other bits of this register, so I find that writing 0xDD7 enables the signal and 0x9D7 disables it. The board may behave strangely for other values. You will still have to connect the test signal to a phonon or QET channel to see it, however. I think the test signal defaults to ON when the board boots under this firmware version. You do NOT need to use the DDSControlPin in register 0x3c with the newer firmware.

Older firmware (pre-April 2014): Sten confirms that under the current older there is no way to stop the test signal. As far as controlling the signal goes, it would be far, far better if there were just one bit that could be set for “test signal on” and “test signal off”. Since I cannot change the frequency of the test signal without turning it off, the current implementation means I cannot easily change the frequency without rebooting the whole DCRC!

Newer firmware (post-April 2014): You can stop the test signal by writing 0x9D7 to register 0x3d when using the newer firmware.

By setting the bit TowerXX/Settings/DCRCYY/General/TriggerSource to on, the board will trigger on inflections of the test signal. I find that when I run “rt”, I always get exactly one trigger! Maybe it's even the case that running “rt” causes the test signal to fire eactly once.

1. With older firmware it's not possible to stop the test signal without rebooting the board, although we can of course disconnect it from the phonon and/or QET channel, and decide to trigger or not trigger on it. The new firmware that Sten produced in April 2014 fixes this.
2. Only a triangle waveform is available. At a minimum a square wave option is also needed.
3. The frequency cannot be changed while the test signal is running when using the older firmware. This would be tolerable if there were an easy way to stop it.
4. The interface to the test signal generator in the DCRC is very hard to use with the older firmware. There needs to be one bit that turns it on or off (as a level setting). Another bit (or set of bits) is needed to select between different waveform shapes (although right now there is only one option). The frequency and amplitude should be changeable even while the test signal is running. All of the obselete emulation of the AD5932 chip should just be stripped out.
5. There is no option to apply a DC offset to the test signal.
6. Better documentation is needed for how to calibrate and set the pulse parameters.

Although Sten's April 2014 firmware version helps a lot, it is not compatible with RevC boards, only RevC.1.

wr 301a 59 2098
W 301A 0059 2098 0
wr 301b 5a 20a3
W 301B 005A 20A3 0
dsav 1
Setup saved to ATMEL Page 1
fmr 1
Ptr   A16  D16   A16  D16   (cmd syntax) Wr(3000-3041h) A16(aaaa) D16(dddd)
3000  0034 0800  0035 0800
3002  0036 0800  0037 0800
3004  0038 0500  0039 0500
3006  003A 0500  003B 0500
3008  0047 8000  0048 8000
300A  0049 8000  004A 8000
300C  004B 8000  004C 8000
300E  004D 8000  004E 8000
3010  0051 8000  0052 8000
3012  0053 8000  0054 8000
3014  0055 8000  0056 8000
3016  0057 8000  0058 8000
3018  0045 7474  004F 7474
301A  0059 2098  005A 20A3
301C  003C 0000  003D 0DD7
301E  003E 0002  003F 0000
3020  0040 0000  0041 0002
3022  0042 0022  0043 0000
3024  0015 00B0  0044 0160
3026  0033 0000  0033 2000
3028  0030 0800  0000 0000 <-- (A16==0) marks end of list
302A  FFFF FFFF  FFFF FFFF
302C  FFFF FFFF  FFFF FFFF
302E  FFFF FFFF  FFFF FFFF
3030  FFFF FFFF  FFFF FFFF
3032  FFFF FFFF  FFFF FFFF
3034  FFFF FFFF  FFFF FFFF
3036  FFFF FFFF  FFFF FFFF
3038  FFFF FFFF  FFFF FFFF
303A  FFFF FFFF  FFFF FFFF
303C  FFFF FFFF  FFFF FFFF
303E  FFFF FFFF  FFFF FFFF
3040  FFFF FFFF  FFFF FFFF

wr 3008 47 7b3b
W 3008 0047 7B3B 0
wr 300c 4b 8080
W 300C 004B 8080 0
wr 3010 51 7700
W 3010 0051 7700 0
wr 3014 55 7b52
W 3014 0055 7B52 0
dsav 1
Setup saved to ATMEL Page 1
fmr 1
Ptr   A16  D16   A16  D16   (cmd syntax) Wr(3000-3041h) A16(aaaa) D16(dddd)
3000  0034 0800  0035 0800
3002  0036 0800  0037 0800
3004  0038 0500  0039 0500
3006  003A 0500  003B 0500
3008  0047 7B3B  0048 8000
300A  0049 8000  004A 8000
300C  004B 8080  004C 8000
300E  004D 8000  004E 8000
3010  0051 7700  0052 8000
3012  0053 8000  0054 8000
3014  0055 7B52  0056 8000
3016  0057 8000  0058 8000
3018  0045 7474  004F 7474
301A  0059 2098  005A 20A3
301C  003C 0000  003D 0DD7
301E  003E 0002  003F 0000
3020  0040 0000  0041 0002
3022  0042 0022  0043 0000
3024  0015 00B0  0044 0160
3026  0033 0000  0033 2000
3028  0030 0800  0000 0000 <-- (A16==0) marks end of list
302A  FFFF FFFF  FFFF FFFF
302C  FFFF FFFF  FFFF FFFF
302E  FFFF FFFF  FFFF FFFF
3030  FFFF FFFF  FFFF FFFF
3032  FFFF FFFF  FFFF FFFF
3034  FFFF FFFF  FFFF FFFF
3036  FFFF FFFF  FFFF FFFF
3038  FFFF FFFF  FFFF FFFF
303A  FFFF FFFF  FFFF FFFF
303C  FFFF FFFF  FFFF FFFF
303E  FFFF FFFF  FFFF FFFF
3040  FFFF FFFF  FFFF FFFF

wr 301a 59 1ff2
W 301A 0059 1FF2 0
wr 301b 5a 2003
W 301B 005A 2003 0
dsav 1
Setup saved to ATMEL Page 1
fmr 1
Ptr   A16  D16   A16  D16   (cmd syntax) Wr(3000-3041h) A16(aaaa) D16(dddd)
3000  0034 07C0  0035 07E0
3002  0036 0800  0037 0800
3004  0038 0500  0039 0500
3006  003A 0500  003B 0500
3008  0047 8000  0048 8000
300A  0049 8000  004A 8000
300C  004B 8000  004C 8000
300E  004D 8000  004E 8000
3010  0051 8000  0052 8000
3012  0053 8000  0054 8000
3014  0055 8000  0056 8000
3016  0057 8000  0058 8000
3018  0045 7474  004F 7474
301A  0059 1FF2  005A 2003
301C  003C 4000  003D 0DD7
301E  003E 0002  003F 0000
3020  0040 0000  0041 0002
3022  0042 0022  0043 0000
3024  0015 00B0  0044 0160
3026  0033 0000  0033 2000
3028  0030 0800  0033 2000
302A  FFFF FFFF  FFFF FFFF
302C  FFFF FFFF  FFFF FFFF
302E  FFFF FFFF  FFFF FFFF
3030  FFFF FFFF  FFFF FFFF
3032  FFFF FFFF  FFFF FFFF
3034  FFFF FFFF  FFFF FFFF
3036  FFFF FFFF  FFFF FFFF
3038  FFFF FFFF  FFFF FFFF
303A  FFFF FFFF  FFFF FFFF
303C  FFFF FFFF  FFFF FFFF
303E  FFFF FFFF  FFFF FFFF
3040  FFFF FFFF  FFFF FFFF

wr 3008 47 771d
W 3008 0047 771D 0
wr 300c 4b 6d45
W 300C 004B 6D45 0
wr 3010 51 7bea
W 3010 0051 7BEA 0
wr 3014 55 8300
W 3014 0055 8300 0
dsav 1
Setup saved to ATMEL Page 1
fmr 1
Ptr   A16  D16   A16  D16   (cmd syntax) Wr(3000-3041h) A16(aaaa) D16(dddd)
3000  0034 07C0  0035 07E0
3002  0036 0800  0037 0800
3004  0038 0500  0039 0500
3006  003A 0500  003B 0500
3008  0047 771D  0048 8000
300A  0049 8000  004A 8000
300C  004B 6D45  004C 8000
300E  004D 8000  004E 8000
3010  0051 7BEA  0052 8000
3012  0053 8000  0054 8000
3014  0055 8300  0056 8000
3016  0057 8000  0058 8000
3018  0045 7474  004F 7474
301A  0059 1FF2  005A 2003
301C  003C 4000  003D 0DD7
301E  003E 0002  003F 0000
3020  0040 0000  0041 0002
3022  0042 0022  0043 0000
3024  0015 00B0  0044 0160
3026  0033 0000  0033 2000
3028  0030 0800  0033 2000
302A  FFFF FFFF  FFFF FFFF
302C  FFFF FFFF  FFFF FFFF
302E  FFFF FFFF  FFFF FFFF
3030  FFFF FFFF  FFFF FFFF
3032  FFFF FFFF  FFFF FFFF
3034  FFFF FFFF  FFFF FFFF
3036  FFFF FFFF  FFFF FFFF
3038  FFFF FFFF  FFFF FFFF
303A  FFFF FFFF  FFFF FFFF
303C  FFFF FFFF  FFFF FFFF
303E  FFFF FFFF  FFFF FFFF
3040  FFFF FFFF  FFFF FFFF

wr 301a 59 2091
W 301A 0059 2091 0
wr 301b 5a 207d
W 301B 005A 207D 0
dsav 1
Setup saved to ATMEL Page 1
fmr 1
Ptr   A16  D16   A16  D16   (cmd syntax) Wr(3000-3041h) A16(aaaa) D16(dddd)
3000  0034 0800  0035 0800
3002  0036 0800  0037 0800
3004  0038 0500  0039 0500
3006  003A 0500  003B 0500
3008  0047 8000  0048 8000
300A  0049 8042  004A 8000
300C  004B 8000  004C 8000
300E  004D 7FF8  004E 8000
3010  0051 8000  0052 8000
3012  0053 7FA4  0054 8000
3014  0055 8000  0056 8000
3016  0057 7FD8  0058 8000
3018  0045 7474  004F 7474
301A  0059 2091  005A 207D
301C  003C 0000  003D 0DD7
301E  003E 0002  003F 0000
3020  0040 0000  0041 0002
3022  0042 0022  0043 0000
3024  0015 0001  0044 0160
3026  0033 0000  0033 2000
3028  0030 0000  0000 0000 <-- (A16==0) marks end of list
302A  FFFF FFFF  FFFF FFFF
302C  FFFF FFFF  FFFF FFFF
302E  FFFF FFFF  FFFF FFFF
3030  FFFF FFFF  FFFF FFFF
3032  FFFF FFFF  FFFF FFFF
3034  FFFF FFFF  FFFF FFFF
3036  FFFF FFFF  FFFF FFFF
3038  FFFF FFFF  FFFF FFFF
303A  FFFF FFFF  FFFF FFFF
303C  FFFF FFFF  FFFF FFFF
303E  FFFF FFFF  FFFF FFFF
3040  FFFF FFFF  FFFF FFFF

Charge channel digitizer: AD7621, 16-bit, 62.5uV/ADC bin

Phonon digitizer: ±1.25V 14-bit, 152.58789uV/ADC bin

3kOhm resistors on LED bias circuit R75 and R20 on DCRC33 are replaced with 2kOhm resistors. The same modification was done on DCRC30 too. DCRC32 is modified too

LED1 and LED2 outputs can be probed at the left end of R21 and R76.

DCRC30, 32, and 33 have the same processor LM3S5B91

DAC test points: There are 16 yellow/black capacitors at the lower left corner of the board in four groups. From left to right, the four groups are for phonon channel B, A, D, and C respectively. In each group, from left to right, the top end of the capacitor connect to the DAC voltages of QET bias, SQUID bias, lock point, and Driver offset of a phonon channel. The voltages are not scaled yet, the range is from 0V to 2.048V.

U20: Pin 9 → VGA D, Pin 16 → VGA C. U21: Pin 9 → VGA B, Pin 16 → VGA A.

Left end of R168: Qi offset. Left end of R170: Qo offset.

The command 'wr 33 2000' in flash memory page 1 may not always work. Sometimes the command need to be resent again.

Qi/Qo theoretical min/max = 13.52V

U29 Pin6 voltage reference: 4.095V

U27 Pin7→Qo, Pin8→Qi

R23→Qi, R25→Qo

http://www.hep.umn.edu/cdms/cdms_restricted/K100/DCRC/DCRC_FPGA/usb_dev_serial_win2k.inf

http://www.hep.umn.edu/cdms/cdms_restricted/K100/DCRC/DCRC_FPGA/Flash%20memory.htm

http://www.hep.umn.edu/cdms/cdms_restricted/K100/DCRC/v3/debug/DAQ%20Debug.htm