−Table of Contents
DCRC v2
Hardware
Charge digitizer: AD7621, 16 bit, 62.5uV/ADC bin.
Board info
id CDMS_Code_Vers :0.03 Compile_date :Jul 7 2009 IAR_Compiler_Ver :4.41 Socket 0 Port(d) : 5000 MSS=1460 Socket 1 Port(d) : 5001 MSS=1460 Socket 2 Port(d) : 5002 MSS=1460 Socket 3 Port(d) : 1003 MSS=1460 Socket 4 Port(d) : 0 MSS=0 Socket 5 Port(d) : 0 MSS=0 Socket 6 Port(d) : 0 MSS=0 Socket 7 Port(d) : 0 MSS=0 |
CDMS DAQ Commands, hex(h), dec(d), (use SET cmd for net info). Main RDB addr cnt Read DATA Binary, Addr(hex), ByteCnt(hex)(even cnt). RD addr cnt mod Read Adr(h) ASCII, WrdCnt(h)(def=1), Wrds/Line(def=8). WR addr data Write Addr ASCII, Data16 (word write). Misc DREC s Device Recall,(s= Setup 1-10d, 1=Boot) FLASH->SETUP. DSAV s Device Save, (s= Setup 1-10d, 1=Boot) SETUP->FLASH. FL Flash Load (to ATMEL MEMORY) using Altera Binary File(*.rbf). FMR n Flash Mem Read (n=page), reads 264 bytes from ATMEL FLASH. ID Display Network Setup. MO Monitor ADC Channels & Temperature. QUIT s Close Network Socket, s=socket 0-2, no param=this socket. RESET Hardware Reset of Ethernet, FPGA, then soft restart. SBR b Set Baud Rate,USB, 1=19.2K, 2=38.4K, 3=57K, 4=115K, 5=230K SET Set Network Regs, Sockets, Ports, and serial number (SAVE). SOCK Display Network Socket Status, Enabled 0-2, Disabled 3-7. |
Calibration table
| Quantity | Address | Decimal | Hex | Output |
|---|---|---|---|---|
| Qi Bias | 0x5A | -0.06 | 1FD7 | 0.03 mV |
| Qo Bias | 0x59 | -0.02 | 1FF0 | -0.6 mV |
| SQUID Bias A | 0x49 | -0.93 | 7F6 | ±0.1 mV |
| SQUID Bias B | 0x4D | 0.83 | 808 | -0.9 mV |
| SQUID Bias C | 0x53 | -0.24 | 7FD | -0.5 mV |
| SQUID Bias D | 0x57 | -0.24 | 7FD | -0.5 mV |
| QET Bias A | 0x4A | 375 | 281C | 0.6 mV |
| QET Bias B | 0x4E | 367 | 27F1 | 0.1 mV |
| QET Bias C | 0x54 | 373.7 | 2815 | -0.5 mV |
| QET Bias D | 0x58 | -15 | 7EE | 0.1 mV |
| VGA gain phA | 0x38 | |||
| VGA gain phB | 0x39 | |||
| VGA gain phC | 0x3A | |||
| VGA gain phD | 0x3B | |||
| Test signal generator control | 0x3C | 0 | ||
| Driver offset A | 0x47 | 0x800 | ||
| Driver offset B | 0x4B | 0x800 | ||
| Driver offset C | 0x51 | 0x800 | ||
| Driver offset D | 0x55 | 0x800 | ||
| SQUID lock point A | 0x48 | 0x800 | ||
| SQUID lock point B | 0x4C | 0x800 | ||
| SQUID lock point C | 0x52 | 0x800 | ||
| SQUID lock point D | 0x56 | 0x800 |