−Table of Contents
DCRC v1
Hardware
Charge digitizer: ADS1602 16-bit, resolution 91.6uV/ADC bin
DCRC v1 Settings
Preset 2 at 2010-05-10
| Q Inner (V) | 3 |
|---|---|
| Q Outer (V) | 3 |
| Channel | Frontend Gain | Output Gain | Feedback Null | Driver Offset | SQUID Bias (uA) | Lockpoint (mV) | QET Bias(uA) |
|---|---|---|---|---|---|---|---|
| A | 7 | 1 | 0 | 0 | 95 | 3.34 | -136.9 |
| B | 7 | 1 | 0 | 0 | 100 | 3.4 | -120.1 |
| C | 7 | 1 | 0 | 0 | 92 | 3.2 | -120.1 |
| D | 7 | 1 | 0 | 0 | 95 | 3.5 | -120.1 |
DCRC v1
DCRC vi bugs
- control and readout vi share the same set of subvi with different connection ports
- lookback time spikes
- DCRC settings from and to files
- connection problem
DCRC setup
- A crossover Ethernet cable is needed to connect DCRC and computer (doesn't need if at least one end is Gigabit enabled). http://cdms.berkeley.edu/cdms_restricted/elog/DCRC+Development/12
- Connect DCRC via USB http://cdms.berkeley.edu/cdms_restricted/elog/DCRC+Development/52
- Change Ethernet settings http://cdms.berkeley.edu/cdms_restricted/elog/DCRC+Development/51
set
1) G/W IP ADDRESS :192.168.0.1 'Use dots or spaces between numbers'
2) SUBNET MASK :255.255.255.0
3) MAC ADDRESS :00.80.55.bd.00.13
4) LOCAL IP ADDRESS :192.168.0.2
5) LOCAL DAQ Port0 :5000 (d) 'Line Mode'
6) LOCAL DAQ Port1 :5001 (d) 'Line Mode'
7) LOCAL Tel Port :5002 (d) 'Line/Ch Mode, Verbose'
8) Board Serial # :0004 (d)
9) TCP Timeout # :0200 (d) 'Word, (100uS/bit), 10=1mS
10) TCP Retry # :0020 (d) 'Byte, TCP Max Re-Xmits after timeout
11) UDP Port # :5003 (d) 'Local UDP port number
Use cmd 'SET' as SET 1 131.225.55.200 or SET 2 00.80.55.bd.00.36, ...
Use cmd 'SAVE' when finished. The next RESET will use this saved setup.
To restore defaults, set SerNum=0 (cmd 'SET 8 0'), then RESET.
Defaults... will be used while SerNum=0.
New Setup... use cmd(s) SET 1-11, SET 8 SerNum!=0, then SAVE, then RESET.
DCRC ID
id CDMS_Code_Vers : 0.01 Compile_date : Jun 15 2007 IAR_Compiler_Ver : 4.41 MAC ADDRESS : 00.80.55.bd.00.13 SUBNET MASK : 255.255.255.0 G/W IP ADDRESS : 192.168.0.1 LOCAL IP ADDRESS : 192.168.0.2 Local Port 0 (d): 5000 Local Port 1 (d): 5001 Local Port 2 (d): 5002 Local Port 3 (d): 5003 MSS REGS (0-3)(d): 1460 1460 1460 1472
DCRC commands
help CDMS DAQ Commands, hex(h), dec(d), (use SET cmd for net info). Main DEVD n m Dev Display, n=1 adds text info, m=1 for calibration data Dev50. DEVR dev addr Dev Read, dev, addr, returns=16Bit data. DEVW dev adr dat Dev Write, dev, addr, Data16. DREC s Dev Recall,(s= Setup 1-10d, 1=Boot) FLASH->RAM. DSAV s Dev Save, (s= Setup 1-10d, 1=Boot) RAM->FLASH. RDB addr cnt Read FPGA Binary, Addr(h), ByteCnt(h)(def=1)(even count). RDF addr cnt mod Read FPGA Asc, Adr(h), WrdCnt(h)(def=1), Wrds/Line(def=8). WRF addr data Write FPGA, Addr, Data16(word write). Misc FL Flash Load using Altera Binary File(*.rbf). FMR n Flash Mem Read(n=page). ID Display Network Setup. MO Monitor ADC Channels & Temperature. QUIT s Close Network Socket, s=socket 0-2, no param=this socket. RESET Hardware Reset of Ethernet, FPGA, then soft restart. SBAUD b Set USB Baud, 1=19.2K, 2=38.4K, 3=57K, 4=115K, 5=230K SET Set Network Regs, Sockets, Ports, and serial number (SAVE). SOCK Display Network Socket Status, sockets 0-3. Calibration DEVR 50 adr Dev50 Display cal. memory data word, adr=0-83h,(def=0). DEVW 50 adr dat Dev50 Write cal. memory data word, adr=0-83h, dat=16Bit. DSAV 50 Dev50 Save cal. memory data block to Flash.
DCRC calibration
| DCRC calibration constants |
|---|
devd 1 1 Dev50.Ch00=2000 QinnerOffset Qinner bias is zero with this setting. [DAC] Dev50.Ch01=05B9 QinnerSlope The Qinner bias setting slope [uV/DAC] Dev50.Ch02=2000 QouterOffset Qouter bias is zero with this setting. [DAC] Dev50.Ch03=05B9 QouterSlope The Qouter bias setting slope [uV/DAC] Dev50.Ch04=2004 QETOffsetA Ch A QET bias is zero with this setting. [DAC] Dev50.Ch05=46B4 QETSlopeA Ch A QET bias setting slope. [10 pA/DAC] Dev50.Ch06=0808 SqOffsetA Ch A SQUID bias is zero with this setting. [DAC] Dev50.Ch07=2714 SqSlopeA Ch A SQUID bias setting slope. [10 pA/DAC] Dev50.Ch08=0802 LockOffsetA Ch A Lockpoint is zero with this setting. [DAC] Dev50.Ch09=1A14 LockSlopeA Ch A Lockpoint setting slope. [uV/DAC] Dev50.Ch0A=07FE DriveOffsetA Ch A Driver Offset is zero with this setting. [DAC] Dev50.Ch0B=084D DriveSlopeA Ch A Driver Offset setting slope. [-uV/DAC] Dev50.Ch0C=0843 NullOffsetA Ch A Offset Null is zero with this setting. [DAC] Dev50.Ch0D=0121 NullSlopeA Ch A Offset Null setting slope. [uV/DAC] Dev50.Ch0E=1FF9 QETOffsetB Ch B QET bias is zero with this setting. [DAC] Dev50.Ch0F=4840 QETSlopeB Ch B QET bias setting slope. [10 pA/DAC] Dev50.Ch10=0802 SqOffsetB Ch B SQUID bias is zero with this setting. [DAC] Dev50.Ch11=2700 SqSlopeB Ch B SQUID bias setting slope. [10 pA/DAC] Dev50.Ch12=0817 LockOffsetB Ch B Lockpoint is zero with this setting. [DAC] Dev50.Ch13=1A27 LockSlopeB Ch B Lockpoint setting slope. [uV/DAC] Dev50.Ch14=080E DriveOffsetB Ch B Driver Offset is zero with this setting. [DAC] Dev50.Ch15=083D DriveSlopeB Ch B Driver Offset setting slope. [-uV/DAC] Dev50.Ch16=08B5 NullOffsetB Ch B Offset Null is zero with this setting. [DAC] Dev50.Ch17=0127 NullSlopeB Ch B Offset Null setting slope. [uV/DAC] Dev50.Ch18=1FFB QETOffsetC Ch C QET bias is zero with this setting. [DAC] Dev50.Ch19=4867 QETOffsetC Ch C QET bias is zero with this setting. [DAC] Dev50.Ch1A=080F QETSlopeC Ch C QET bias setting slope. [10 pA/DAC] Dev50.Ch1B=269B SqOffsetC Ch C SQUID bias is zero with this setting. [DAC] Dev50.Ch1C=081A SqSlopeC Ch C SQUID bias setting slope. [10 pA/DAC] Dev50.Ch1D=1A02 LockOffsetC Ch C Lockpoint is zero with this setting. [DAC] Dev50.Ch1E=0804 LockSlopeC Ch C Lockpoint setting slope. [uV/DAC] Dev50.Ch1F=0873 DriveOffsetC Ch C Driver Offset is zero with this setting. [DAC] Dev50.Ch20=083C DriveSlopeC Ch C Driver Offset setting slope. [-uV/DAC] Dev50.Ch21=011C NullOffsetC Ch C Offset Null is zero with this setting. [DAC] Dev50.Ch22=2000 NullSlopeC Ch C Offset Null setting slope. [uV/DAC] Dev50.Ch23=482D QETOffsetD Ch D QET bias is zero with this setting. [DAC] Dev50.Ch24=07FD QETSlopeD Ch D QET bias setting slope. [10 pA/DAC] Dev50.Ch25=26EF SqOffsetD Ch D SQUID bias is zero with this setting. [DAC] Dev50.Ch26=080A SqSlopeD Ch D SQUID bias setting slope. [10 pA/DAC] Dev50.Ch27=1A21 LockOffsetD Ch D Lockpoint is zero with this setting. [DAC] Dev50.Ch28=07FC LockSlopeD Ch D Lockpoint setting slope. [uV/DAC] Dev50.Ch29=0859 DriveOffsetD Ch D Driver Offset is zero with this setting. [DAC] Dev50.Ch2A=08D1 DriveSlopeD Ch D Driver Offset setting slope. [-uV/DAC] Dev50.Ch2B=012C NullOffsetD Ch D Offset Null is zero with this setting. [DAC] Dev50.Ch2C=FFFF NullSlopeD Ch D Offset Null setting slope. [uV/DAC] Dev50.Ch2D=FFFF LEDSlope1 LED 1 current setting slope. [uA/DAC] Dev50.Ch2E=FFFF LEDSlope2 LED 2 current setting slope. [uA/DAC] Dev50.Ch2F=FFFF FBGain Feedback gain with PGA set to 1. Dev50.Ch30=FFFF OutGain Output gain with PGA set to 1. Dev50.Ch31=FFFF |
| DCRC calibration by HP3478A measurements | |||
|---|---|---|---|
| Quantity | Decimal | Hex | Output |
| Qi Bias | 0.04 | 201E | -0.8 mV |
| Qo Bias | -0.04 | 1FE3 | -0.3 mV |
| SQUID Bias A | 0.83 | 808 | 0.1 mV |
| SQUID Bias B | 0.24 | 802 | -0.3 mV |
| SQUID Bias C | 1.51 | 80F | -0.8 mV |
| SQUID Bias D | -0.24 | 7FD | -0.1 mV |
| QET Bias A | 34.1 | 20BC | 0.05 mV |
| QET Bias B | -1.7 | 1FF6 | 0.8 mV |
| QET Bias C | -1.2 | 1FF9 | 0.05 mV |
| QET Bias D | -0.1 -0.3 | 1FFF 1FFE | 0.26 mV -0.26 mV |
DCRC documents
More info can be found at http://ppd.fnal.gov/experiments/cdms/
Breakout box and DCRC testing points
DCRC pin out is the same as IO cable in the Breakout box pin out. Excel version
DCRC Calibration Table
| Quantity | Decimal | Hex | Output |
|---|---|---|---|
| Qi Bias | 0.04 | 201E | -0.8 mV |
| Qo Bias | -0.04 | 1FE3 | -0.3 mV |
| SQUID Bias A | 0.83 | 808 | 0.1 mV |
| SQUID Bias B | 0.24 | 802 | -0.3 mV |
| SQUID Bias C | 1.51 | 80F | -0.8 mV |
| SQUID Bias D | -0.24 | 7FD | -0.1 mV |
| QET Bias A | 34.1 | 20BC | 0.05 mV |
| QET Bias B | -1.7 | 1FF6 | 0.8 mV |
| QET Bias C | -1.2 | 1FF9 | 0.05 mV |
| QET Bias D | -0.1 -0.3 | 1FFF 1FFE | 0.26 mV -0.26 |
Set the above settings and Frontend Gain = 0, Output Gain = 1, Feedback Null = 0, Driver Offset = 0, Openloop, and Preamp on all channels as the Preset 1.
DCRC Software Versions
| Version | Comment |
|---|---|
| 20100101 | Modified from 20070423; LED DC offset and ZAP voltage turning off fixed. |
| 20100302 | From Jeter with lookback time fix |
| 20100303 | 20091223 with lookback time fix and auto flashing addition. |